1. Field of the Invention
The present invention relates to a data processing system and, for example, relates to a data processing system that has a burst function to enable a front end to output plural read data in serial, which are read in parallel from a back end including plural data and that can achieve a variety of burst functions.
2. Description of Related Art
As a DRAM (Dynamic Random Access Memory) which is a representative semiconductor memory having a back end and a front end, a synchronous type that performs output of read data or input of write data in synchronization with a clock signal is commonly used. Many of the synchronous DRAMs can perform a burst operation to continuously output plural read data, which are transferred from a back end with a memory function, via a front end in synchronization with a clock signal, or continuously input plural write data via the front end to transfer the data to the back end in synchronization with a clock signal. The number of output bits of continuous read data during a read operation or the number of input bits of continuous write data during a write operation is usually called “burst length”.
Setting of a burst length is usually performed by setting a desired value in a mode register included in a semiconductor memory. However, to change a set value in the mode register, a mode-register set command needs to be executed and therefore the burst length cannot be changed for each access in this method. To solve this problem, Japanese Patent Application Laid-open No. 2006-252668 and U.S. Pat. No. 7,149,824 propose a semiconductor memory that can specify a burst length for each access. U.S. Pat. No. 6,795,889 proposes a semiconductor memory that can set a burst length smaller than the number of prefetch data that are read from a memory cell array as a back end.
However, the present inventors have noted a problem that it is difficult to apply the semiconductor memory described in the above patent documents to semiconductor memories having a data bus with low use efficiency or high-speed semiconductor memories that are recently used. That is, as shown in FIG. 1A of Japanese Patent Application Laid-open No. 2006-252668, when an interval between read accesses 1 and 2 is set rather long, a period in which a data bus is not used occurs from the end of a burst operation corresponding to the read access 1 until the start of a burst operation corresponding to the read access 2, which reduces use efficiency of the data bus. To prevent occurrence of the nonuse period of the data bus, intervals between read accesses 1 to 3 need to be shortened as shown in FIG. 1B of Japanese Patent Application Laid-open No. 2006-252668. However, a memory controller in a current high-speed data processing system cannot issue commands at such short intervals. Furthermore, even if the controller can issue the commands at the short intervals, a back end having a lower operation frequency than that of a front end cannot follow. Dealing therewith by increasing the number of prefetches of plural data to be applied to a well-known back end has a limitation due to an increase in power consumption, increases in the number of internal data buses and the number of internal pipelines and the like. For example, a clock frequency of a currently fastest DRAM (a frequency of a data processing system) is about 1 GHz and, in this case, one clock cycle is 1 ns (nanosecond). This indicates that setting of the interval between the read accesses 2 and 3 to one clock cycle as shown in FIG. 1B of Japanese Patent Application Laid-open No. 2006-252668 is unfeasible in the technical concept of the current data processing system. Furthermore, it is desired that a frequency of a data processing system higher than 1 GHz, be also handled.
In addition, the semiconductor device and the data processing system described in the above patent documents can merely change a burst length for each access and cannot realize a variety of burst functions, for example, to enable the front end to rearrange plural read data to be burst-outputted.